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| KS8999 Micrel KS8999 Integrated 9-Port 10/100 Switch with PHY and Frame Buffer Rev. 1.14 General Description The KS8999 contains eight 10/100 physical layer transceivers, nine MAC (Media Access Control) units with an integrated layer 2 switch. The device runs in two modes. The first mode is an eight port integrated switch and the second is as a nine port switch with the ninth port available through an MII (Media Independent Interface). Useful configurations include a stand alone eight port switch as well as a eight port switch with a routing element connected to the extra MII port. The additional port is also useful for a public network interfacing.The KS8999 is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset time.On the media side, the KS8999 supports 10BaseT, 100BaseTX and 100BaseFX as specified by the IEEE 802.3 committee. Physical signal transmission and reception are enhanced through use of analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com. Functional Diagram Look Up Engine (1K Entries) Queue Priority Management Buffer Management SRAM Buffers FIFO, Flow Control, VLAN and Priority M A C 1 M A C 2 M A C 3 M A C 4 M A C 5 M A C 6 M A C 7 M A C 8 M A C 9 P H Y 1 P H Y 2 P H Y 3 P H Y 4 P H Y 5 P H Y 6 P H Y 7 P H Y 8 MII / SNI (exclusive) External Interface M I I MRXD[3:0] MRXDV MCOL MCRS MTXD[3:0] MTXEN MTXER MTXC MRXC MRXD[0] MRXDV MCOL EEPROM / Processor Interface SCL SDA LED and Programming Interface LED[1][3:0] LED[2][3:0] LED[3][3:0] LED[4][3:0] LED[5][3:0] LED[6][3:0] LED[7][3:0] LED[8][3:0] LED[9][3:0] S N I MTXD[0] MTXEN MTXC MRXC Micrel, Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com January 2005 1 KS8999 KS8999 Micrel Features * 9 port (8+1) 10/100 integrated switch with eight physical layer transceivers and one MII/SNI interface * Advanced Ethernet Switch with internal frame buffer - 128K Byte of SRAM on chip for frame buffering - 2.0Gbps high performance memory bandwidth - Wire speed reception and transmission - Integrated address look-up engine, supports 1K absolute MAC addresses - Automatic address learning, address aging and address migration * Advanced Switch Features - Supports 802.1p priority and port based priority - Supports port based VLAN - Supports 1536 byte frame for VLAN tag - Supports DiffServ priority, 802.1p based priority or port based priorityo broadcast storm protection * Proven transceiver technology for UTP and fiber operation - 10BaseT, 100BaseTX and 100BaseFX modes of operation - Supports for UTP or fiber on all 8-ports - Indicators for link, activity, full/half-duplex and speed - Hardware based 10/100, full/half, flow control and auto-negotiation - Individual port forced modes (full duplex, 100BaseTX) when auto-negotiation is disabled - Full duplex IEEE 802.3x flow control - Half-duplex back pressure flow control * Supports MDI/MDI-X auto crossover * External MAC interface (MII or 7-wire) for router applications * Unmanaged operation via strapping or EEPROM at system reset time (see Reset Reference Circuit section) * Comprehensive LED support * Single 2.0V power supply with options for 2.5V and 3.3V I/O * 900 mA (1.80W) including physical transmit drivers * Supports both commercial and industry temperature - Commercial temperature range: 0C to +70C (KS8999) - Industrial temperature range: -40C to +85C (KS8999I) * Supports lead free products: - Commercial temperature range: 0C to +70C (KSZ8999) - Industrial temperature range: -40C to +85C (KSZ8999I) * Available in 208-pin PQFP package Ordering Information Part Number KS8999 KS8999I KSZ8999 KSZ8999I Temperature Range 0C to +70C -40C to +85C 0C to +70C -40C to +85C Package 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP KS8999 2 January 2005 KS8999 Micrel Revision History Revision 1.00 1.01 Date 11/27/00 03/30/01 Summary of Changes Preliminary Release Update maximum frame size Update EEPROM priority descriptions Update I/O pin definitionUpdate I/O descriptions Update Electrical Characteristics Correct timing information Add MDI/MDI-X description Change electrical requirements Correct I/O descriptions Update PLL clock information Update timing information Correct LED[6][1:0] to float configuration Add reverse and forward timing Correct optional CPU timing Update Optional CPU interface Correct I/O description for MCOL and MCRS Correct pin 174 and 175 description Correct default to floating for pin 174 Change pin 87 TEST[3] to AUTOMDIX for enable/disable of auto MDI-MDIX function Add KS8999I industrial temperature Update non-periodic blinking in Mode 1 of LED[1:9][0] Add MRXD[0] description Changed Vcc from 2.00 to 2.10 (typical) Added FEF disable to T[4] pin #173 Convert to new format. Correct pin type description. Correct selection of reference oscillator/crystal spec. Insert recommended reset circuit. Added lead free and Industrial temperature packages. 1.02 1.03 1.04 1.05 1.06 1.07 04/20/01 05/11/01 06/22/01 0/6/25/01 07/25/01 08/09/01 1.08 1/14/02 1.09 1.10 6/18/02 2/27/03 1.11 1.12 1.13 1.14 5/12/03 8/29/03 1/19/05 1/31/05 January 2005 3 KS8999 KS8999 Micrel Table of Contents System Level Applications ......................................................................................................................................... 6 Pin Description ............................................................................................................................................................ 7 I/O Grouping ........................................................................................................................................................... 13 I/O Descriptions ......................................................................................................................................................... 13 Pin Configuration ...................................................................................................................................................... 19 Functional Overview: Physical Layer Transceiver ................................................................................................ 20 100BaseTX Transmit ........................................................................................................................................... 20 100BaseTX Receive ............................................................................................................................................ 20 PLL Clock Synthesizer ......................................................................................................................................... 20 Scrambler/De-scrambler (100BaseTX only) ........................................................................................................ 20 100BaseFX Operation ......................................................................................................................................... 20 100BaseFX Signal Detection ............................................................................................................................... 20 100BaseFX Far End Fault ................................................................................................................................... 20 10BaseT Transmit ............................................................................................................................................... 20 10BaseT Receive ................................................................................................................................................ 20 Power Management ............................................................................................................................................. 21 Power Save Mode ........................................................................................................................................ 21 MDI/MDI-X Auto Crossover ................................................................................................................................. 21 Auto-Negotiation .................................................................................................................................................. 21 Functional Overview: Switch Core .......................................................................................................................... 22 Address Look-Up ................................................................................................................................................. 22 Learning ........................................................................................................................................................... 22 Migration ........................................................................................................................................................... 22 Aging ........................................................................................................................................................... 22 Forwarding ........................................................................................................................................................... 22 Switching Engine ................................................................................................................................................. 22 MAC Operation .................................................................................................................................................... 22 Inter Packet Gap (IPG) ................................................................................................................................ 22 Backoff Algorithm ......................................................................................................................................... 23 Late Collision ............................................................................................................................................... 23 Illegal Frames .............................................................................................................................................. 23 Flow Control ................................................................................................................................................. 23 Half-Duplex Back Pressure .......................................................................................................................... 23 Broadcast Storm Protection ................................................................................................................................. 23 MII Interface Operation .............................................................................................................................................. 24 SNI Interface (7-wire) Operation ............................................................................................................................... 26 Prorammable Features .............................................................................................................................................. 26 Priority Schemes .................................................................................................................................................. 26 Per Port Method ................................................................................................................................................... 26 802.1p Method ..................................................................................................................................................... 26 IPv4 DSCP Method .............................................................................................................................................. 26 Other Priority Considerations ............................................................................................................................... 26 VLAN Operation ......................................................................................................................................................... 27 Station MAC Address ................................................................................................................................................ 27 EEPROM Operation ................................................................................................................................................... 28 Optional CPU Interface ............................................................................................................................................. 28 KS8999 4 January 2005 KS8999 Micrel EEPROM Memory Map .............................................................................................................................................. 29 General Conrol Register .............................................................................................................................. 29 Priority Classification Control: 802.1p Tag Field ......................................................................................... 29 Port 1 Control Register ................................................................................................................................ 29 Port 2 Control Register ................................................................................................................................ 30 Port 3 Control Register ................................................................................................................................ 30 Port 4 Control Register ................................................................................................................................ 30 Port 5 Control Register ................................................................................................................................ 31 Port 6 Control Register ................................................................................................................................ 31 Port 7 Control Register ................................................................................................................................ 32 Port 8 Control Register ................................................................................................................................ 32 Port 9 Control Register ................................................................................................................................ 32 Port 1 VLAN Mask Register ......................................................................................................................... 33 Port 2 VLAN Mask Register ......................................................................................................................... 33 Port 3 VLAN Mask Register ......................................................................................................................... 34 Port 4 VLAN Mask Register ......................................................................................................................... 34 Port 5 VLAN Mask Register ......................................................................................................................... 35 Port 6 VLAN Mask Register ......................................................................................................................... 35 Port 7 VLAN Mask Register ......................................................................................................................... 36 Port 8 VLAN Mask Register ......................................................................................................................... 36 Port 9 VLAN Mask Register ......................................................................................................................... 37 Port 1 VLAN Tag Insertion Value Registers ................................................................................................. 37 Port 2 VLAN Tag Insertion Value Registers ................................................................................................. 37 Port 3 VLAN Tag Insertion Value Registers ................................................................................................. 37 Port 4 VLAN Tag Insertion Value Registers ................................................................................................. 37 Port 5 VLAN Tag Insertion Value Registers ................................................................................................. 38 Port 6 VLAN Tag Insertion Value Registers ................................................................................................. 38 Port 7 VLAN Tag Insertion Value Registers ................................................................................................. 38 Port 8 VLAN Tag Insertion Value Registers ................................................................................................. 38 Port 9 VLAN Tag Insertion Value Registers ................................................................................................. 38 Diff Serve Code Point Registers .................................................................................................................. 38 Station MAC Address Registers .................................................................................................................. 38 Absolute Maximum Ratings ..................................................................................................................................... 39 Operating Ratings ..................................................................................................................................................... 39 Electrical Characteristics (KS8999) ......................................................................................................................... 39 Electrical Characteristics (KS8999I) ........................................................................................................................ 41 Timing Diagrams ....................................................................................................................................................... 42 Reference Circuit ....................................................................................................................................................... 47 4B/5B Coding ........................................................................................................................................................... 49 MLT Coding ........................................................................................................................................................... 50 MAC Frame ........................................................................................................................................................... 50 Selection of Isolation Transformers ........................................................................................................................ 51 Selection of Reference Oscillator/Crystal ............................................................................................................... 51 Qualified Magnetic Lists ........................................................................................................................................... 51 Package Information ................................................................................................................................................. 52 January 2005 5 KS8999 KS8999 Micrel purposes or public network access. The major benefits of using the KS8999 are the lower power consumption, unmanaged operation, flexible configuration, built in frame buffering, VLAN abilities and traffic priority control. Two such applications are depicted below. System Level Applications The KS8999 can be configured to fit either in an eight port 10/ 100 application or as a nine port 10/100 network interface with an extra MII/7-wire port. This MII/7-wire port can be connected to an external processor and used for routing Public Network Access Routing Engine MII or SNI KS8999 8-Port Switch with PHY KS8999 9-Port Switch with PHY 8X Transformer or Fiber Interface 8-Port Stand Alone 8X Transformer or Fiber Interface Or 9-Port with Public Network Interface Figure 1. System Applicastions KS8999 6 January 2005 KS8999 Micrel Type(Note 1) Pwr GND GND Pwr I I O O O O Opd Opd Opd Opd GND Pwr Pwr GND O O GND I I GND Pwr 4 4 4 4 3 3 3 3 Pin Description Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Note 1. Pin Name VDD_RX GND_RX GND_RX VDD_RX RXP[3] RXM[3] AOUT2 DOUT2 TXP[3] TXM[3] QH[5] QH[4] QH[3] QH[2] GND_TX VDD_TX VDD_TX GND-ISO TXP[4] TXM[4] GND_TX RXP[4] RXM[4] GND_RX VDD_RX ISET GND-ISO VDD_RX GND_RX RXP[5] RXM[5] GND_TX TXP[5] TXM[5] Port Pin Function 2.0V for equalizer Ground for equalizer Ground for equalizer 2.0V for equalizer Physical receive signal + (differential) Physical receive signal - (differential) Factory test output Factory test output Physical transmit signal + (differential) Physical transmit signal - (differential) Factory test pin - leave open for normal operation Factory test pin - leave open for normal operation Factory test pin - leave open for normal operation Factory test pin - leave open for normal operation Ground for transmit circuitry 2.0V for transmit circuitry 2.0V for transmit circuitry Analog ground Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry Physical receive signal + (differential) Physical receive signal - (differential) Ground for equalizer 2.0V for equalizer Set physical transmit output current GND Pwr GND I I GND O O 5 5 5 5 Analog ground 2.0V for equalizer Ground for equalizer Physical receive signal + (differential) Physical receive signal - (differential) Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise January 2005 7 KS8999 KS8999 Pin Number 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Note 1. Micrel Pin Name GND-ISO VDD_TX VDD_TX GND_TX QL[2] QL[3] QL[4] QL[5] TXP[6] TXM[6] DOUT AOUT RXP[6] RXM[6] VDD_RX GND_RX GND_RX VDD_RX GND-ISO RXP[7] RXM[7] GND_TX TXP[7] TXM[7] VDD_TX VDD_TX TXP[8] TXM[8] GND_TX RXP[8] RXM[8] GND_RX VDD_RX FXSD[5] FXSD[6] Type(Note 1) GND Pwr Pwr GND Opd Opd Opd Opd O O O O I I Pwr GND GND Pwr GND I I GND O O Pwr Pwr O O GND I I GND Pwr Ipd Ipd 5 6 8 8 8 8 7 7 7 7 6 6 6 6 Port Pin Function Analog ground 2.0V for transmit circuitry 2.0V for transmit circuitry Ground for transmit circuitry Factory test pin - leave open for normal operation Factory test pin - leave open for normal operation Factory test pin - leave open for normal operation Factory test pin - leave open for normal operation Physical transmit signal + (differential) Physical transmit signal - (differential) Factory test output - leave open for normal operation Factory test output - leave open for normal operation Physical receive signal + (differential) Physical receive signal - (differential) 2.0V for equalizer Ground for equalizer Ground for equalizer 2.0V for equalizer Analog ground Physical receive signal + (differential) Physical receive signal - (differential) Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) 2.0V for transmit circuitry 2.0V for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry Physical receive signal + (differential) Physical receive signal - (differential) Ground for equalizer 2.0V for equalizer Fiber signal detect Fiber signal detect Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise KS8999 8 January 2005 KS8999 Pin Number 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Note 1. Micrel Pin Name FXSD[7] FXSD[8] GND_RCV GND_RCV VDD_RCV VDD_RCV GND_RCV GND_RCV VDD_RCV VDD_RCV BTOUT2 CTOUT2 RLPBK MUX[1] MUX[2] TEST[1] TEST[2] AUTOMDIX T[1] T[2] T[3] EN1P SDA SCL VDD GND MTXEN MTXD[3] MTXD[2] MTXD[1] MTXD[0] MTXER MTXC MCOL MCRS Type(Note 1) Ipd Ipd GND GND Pwr Pwr GND GND Pwr Pwr O O I I I I I I Ipu Ipd Ipd Ipd Ipd/O Ipd/O Pwr GND Ipd Ipd Ipd Ipd Ipd Ipd Ipd/O Ipd/O Ipd/O 9 9 9 9 9 9 9 9 9 Port 7 8 Pin Function Fiber signal detect Fiber signal detect Ground for clock recovery circuit Ground for clock recovery circuit 2.0V for clock recovery circuit 2.0V for clock recovery circuit Ground for clock recovery circuit Ground for clock recovery circuit 2.0V for clock recovery circuit 2.0V for clock recovery circuit Factory test pin - leave open for normal operation Factory test pin - leave open for normal operation Enable loop back for testing - pull-down/float for normal operation Factory test pin - float for normal operation Factory test pin - float for normal operation Factory test pin - float for normal operation Factory test pin - float for normal operation Auto MDI/MDIX enable and disable - pull-up/float enable; pull-down disable Factory test pin - float for normal operation Factory test pin - float for normal operation Factory test pin - float for normal operation Enable 802.1p for all ports Serial data from EEPROM or processor Clock for EEPROM or from processor 2.0V for core digital circuitry Ground for digital circuitry MII transmit enable MII transmit bit 3 MII transmit bit 2 MII transmit bit 1 MII transmit bit 0 MII transmit error MII transmit clock MII collision detected MII carrier sense Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise January 2005 9 KS8999 KS8999 Pin Number 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 Note 1. Micrel Pin Name VDD-IO GND GND VDD BIST RST# LED[1][3] LED[1][2] LED[1][1] LED[1][0] LED[2][3] LED[2][2] LED[2][1] LED[2][0] MRXDV MRXD[3] MRXD[2] MRXD[1] MRXD[0] MRXC VDD-IO GND LED[3][3] LED[3][2] LED[3][1] LED[3][0] LED[4][3] LED[4][2] LED[4][1] LED[4][0] VDD GND LED[5][3] LED[5][2] LED[5][1] Type(Note 1) Pwr GND GND Pwr Ipd I Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Opd Opu Opu Opu Opu Ipu/O Pwr GND Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Pwr GND Ipu/O Ipu/O Ipu/O 5 5 5 3 3 3 3 4 4 4 4 1 1 1 1 2 2 2 2 9 9 9 9 9 9 Port Pin Function 2.0V, 2.5V or 3.3V for I/O circuitry Ground for digital circuitry Ground for digital circuitry 2.0V for core digital circuitry Built in self test - tie low for normal operation Reset - active low LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 MII receive data valid MII receive bit 3 MII receive bit 2 MII receive bit 1 MII receive bit 0 MII receive clock 2.0V, 2.5V or 3.3V for I/O circuitry Ground for digital circuitry LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 2.0V for core digital circuitry Ground for digital circuitry LED indicator 3 LED indicator 2 LED indicator 1 Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise KS8999 10 January 2005 KS8999 Pin Number 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 Note 1. Micrel Pin Name LED[5][0] LED[6][3] LED[6][2] LED[6][1] LED[6][0] LED[7][3] LED[7][2] LED[7][1] VDD-IO LED[7][0] LED[8][3] LED[8][2] LED[8][1] LED[8][0] GND GND IO_SWM VDD LED[9][3] LED[9][2] LED[9][1] LED[9][0] MIIS[1] MIIS[0] MODESEL[3] MODESEL[2] MODESEL[1] MODESEL[0] TESTEN SCANEN PRSV CFGMODE T[5] T[4] Reserve Type(Note 1) Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Pwr Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O GND GND Ipu Pwr Ipu/O Ipu/O Ipu/O Ipu/O Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipd Ipu I Ipdthevillage I 9 9 9 9 9 9 7 8 8 8 8 Port 5 6 6 6 6 7 7 7 Pin Function LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 1 2.0V, 2.5V or 3.3V for I/O circuitry LED indicator 0 LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 Ground for digital circuitry Ground for digital circuitry Factory test pin - tie high for normal operation 2.0V for core digital circuitry LED indicator 3 LED indicator 2 LED indicator 1 LED indicator 0 MII mode select bit 1 MII mode select bit 0 Selects LED and test modes Selects LED and test modes Selects LED and test modes Selects LED and test modes Factory test pin - tie low for normal operation Factory test pin - tie low for normal operation Reserve 6KB buffer for priority frames Configures programming interface for EEPROM or processor Factory test pin - float for normal operation F/D = normal operation (default) U = disable FEF Reserved - floating for normal operation Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise January 2005 11 KS8999 KS8999 Pin Number 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Note 1. Micrel Pin Name Reserve X1 X2 VDD_PLLTX GND_PLLTX CTOUT BTOUT VDD_RCV VDD_RCV GND_RCV GND_RCV VDD_RCV VDD_RCV GND_RCV GND_RCV FXSD[1] FXSD[2] FXSD[3] FXSD[4] VDD_RX GND_RX RXP[1] RXM[1] GND_TX TXP[1] TXM[1] VDD_TX VDD_TX TXP[2] TXM[2] GND_TX RXP[2] RXM[2] GND-ISO Type(Note 1) I I O Pwr GND O O Pwr Pwr GND GND Pwr Pwr GND GND Ipd Ipd Ipd Ipd Pwr GND I I GND O O Pwr Pwr O O GND I I GND 2 2 2 2 1 1 1 1 1 2 3 4 Port Pin Function Reserved - floating for normal operation Crystal or clock input Connect to crystal 2.0 V for phase locked loop circuit Ground for phase locked loop circuit Factory test pin - leave open for normal operation Factory test pin - leave open for normal operation 2.0V for clock recovery circuit 2.0V for clock recovery circuit Ground for clock recovery circuit Ground for clock recovery circuit 2.0V for clock recovery circuit 2.0V for clock recovery circuit Ground for clock recovery circuit Ground for clock recovery circuit Fiber signal detect Fiber signal detect Fiber signal detect Fiber signal detect 2.0V for equalizer Ground for equalizer Physical receive signal + (differential) Physical receive signal - (differential) Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) 2.0V for transmit circuitry 2.0V for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry Physical receive signal + (differential) Physical receive signal - (differential) Analog ground Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise KS8999 12 January 2005 KS8999 Micrel I/O Grouping Group Name PHY MII SNI IND UP CTRL TEST PWR Description Physical Interface Media Independent Interface Serial Network Interface LED Indicators Unmanaged Programmable Control and Miscellaneous Test (Factory) Power and Ground I/O Descriptions Group PHY I/O Names RXP[1:8] RXM[1:8] TXP[1:8] TXM[1:8] FXSD[1:8] ISET Active Status Analog Analog H Analog Description Differential inputs (receive) for connection to media (transformer or fiber module) Differential outputs (transmit) for connection to media (transformer or fiber module) Fiber signal detect - connect to fiber signal detect output on fiber module with appropriate voltage divider if needed. Tie low for copper mode. Transmit Current Set. Connecting an external reference resistor to set transmitter output current. This pin connects to a 3K 1% resistor to ground if a transformer with 1:1 turn ratio is used. Four bit wide data bus for receiving MAC frames Receive data valid Receive collision detection Carrier sense Four bit wide data bus for transmitting MAC frames Transmit enable Transmit error MII receive clock MII transmit clock Serial transmit data Transmit enable Serial receive data Receive carrier sense/data valid Collision detection SNI receive clock SNI transmit clock Output (after reset) Mode 0: Speed (on = 100/off = 10) Mode 1: 10/100 + link + activity 10Mb link activity = slow blink (non-periodic blinking) 100Mb link activity = fast blink (non-periodic blinking) Mode 2: Collision (on = collision/off = no collision) Mode 3: Speed (on = 100/off = 10) MII MRXD[0:3] MRXDV MCOL MCRS MTXD[0:3] MTXEN MTXER MRXC MTXC H H H H H H H Clock Clock H H H H H Clock Clock L SNI MTXD[0] MTXEN MRXD[0] MRXDV MCOL MRXC MTXC IND LED[1:9][0] January 2005 13 KS8999 KS8999 Group I/O Names LED[1:9][1] Active Status L Description(Note 1) Output (after reset) Mode 0: Full Duplex (on = full/off = half) Mode 1: Full Duplex (on = full/off = half) Mode 2: Full Duplex (on = full/off = half) Mode 3: Reserved Micrel LED[1:9][2] L Output (after reset) Mode 0: Collision (on = collision/off = no collision) Mode 1: Transmit Activity (on during transmission) Mode 2: Link activity (10Mb mode) Mode 3: Full Duplex + Collision (constant on = full duplex; intermittent on = collision; off = half-duplex with no collision) Output (after reset) Mode 0: Link + Activity When LED is solid "on", it indicates the link is on for both 10 or 100BaseTX, but no data is transmitting or receiving. When LED is solid "off", it indicates the link is off. When LED is blinking, it indicates data is transmitting or receiving for either 10 or 100 BaseTX Mode 1: Receive Activity (on = receiving/off = not receiving) Mode 2: Link activity (100Mb mode) Mode 3: Link + Activity (see description above) LED[1:9][3] L Note: Mode is set by MODESEL[3:0] ; please see description in UP (unmanaged programming) section. UP MODESEL[3:0] H Mode select at reset time. LED mode is selected by using the table below. Note that under normal operation MODESEL[3:2] must be tied low. MODESEL 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LED[1][3] LED[1][2] LED[1][1] Note 1. 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation LED mode 0 LED mode 1 LED mode 2 LED mode 3 Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Used for factory testing Programs auto-negotiation on port 1 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 2 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 3 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up. See "Reference Circuits" section. KS8999 14 January 2005 KS8999 Group I/O Names LED[1][0] LED[2][3] LED[2][2] LED[2][1] LED[2][0] LED[3][3] LED[3][2] LED[3][1] LED[3][0] LED[4][3] LED[4][2] LED[4][1] LED[4][0] LED[5][3] Active Status Description(Note 1) Programs auto-negotiation on port 4 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 5 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 6 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 7 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Programs auto-negotiation on port 8 D = Disable auto-negotiation, F/U = Enable auto-negotiation (default) Micrel Programs port speed on port 1. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 2. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 3. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 4. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 5. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 6. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 7. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port speed on port 8. This is only effective if auto-negotiation is disabled. D = 10Mbps, F/U = 100Mbps (default) Programs port duplex (full/ half) on port 1. This is only effective if auto-negotiation is disabled or if this end has auto- negotiation enabled and the far end has auto negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 2. This is only effective if auto-negotiation is disabled or if this end has auto-negotiation enabled and the far end has autonegotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 3. This is only effective if auto-negotiation is disabled or if this end has auto-negotiation enabled and the far end has autonegotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 4. This is only effective if auto-negotiation is disabled or if this end has auto-negotiation enabled and the far end has autonegotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 5. This is only effective if auto-negotiation is disabled or if this end has auto-negotiation enabled and the far end has auto negotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 6. This is only effective if auto-negotiation is disabled or if this end has auto-negotiation enabled and the far end has autonegotiation disabled. D = Full-duplex, F/U = Half-duplex (default) LED[5][2] LED[5][1] LED[5][0] LED[9][3] LED[9][2] Note 1. All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up. See "Reference Circuits" section. January 2005 15 KS8999 KS8999 Group I/O Names LED[9][1] Active Status Description(Note 1) Micrel Programs port duplex (full / half) on port 7. This is only effective if auto-negotiation is disabled or if this end has auto-negotiation enabled and the far end has autonegotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full / half) on port 8. This is only effective if auto-negotiation is disabled or if this end has auto-negotiation enabled and the far end has autonegotiation disabled. D = Full-duplex, F/U = Half-duplex (default) Programs back-off aggressiveness for half-duplex mode D = Less aggressive back-off, F/U = More aggressive back-off (default) Programs retries for frames that encounter collisions. D = Drop frame after 16 collisions, F/U = Continue sending frame regardless of the number of collisions (default) Reserved - use float configuration Programs flow control D = No flow control, F/U = Flow control enabled (default) Programs broadcast storm protection. D = 5% broadcast frames allowed, F/U = Unlimited broadcast frames (default) Programs buffer sharing feature. D = Equal amount of buffers per port (113 buffers), F/U = Share buffers up to 512 buffers on a single port (default) Reserved - use float configuration Programs address aging. D = Aging disabled, F/U = Enable 5 minute aging (default) Programs frame length enforcement. D = Max length for VLAN is 1522 bytes and without VLAN is 1518 bytes F/U = Max length is 1536 bytes (default) Reserved Programs half-duplex back pressure. D = No half-duplex back pressure, F/U = Half-duplex back pressure enabled (default) Programs port 9 speed D = 10Mbps, F/U = 100Mbps (default) Programs port 9 duplex D = Half-duplex, F/U = Full duplex (default) Programs port 9 flow control D = Flow control, F/U = No flow control (default) D = reserved, F/U = normal operation (default) H Enable 802.1p for all ports - this enables QoS based on the priority field in the layer 2 header. 0 = 802.1p selected by port in EEPROM 1 = Use 802.1p priority field unless disabled in EEPROM LED[9][0] LED[6][3] LED[6][2] LED[6][1:0] LED[7][3] LED[7][2] LED[7][1] LED[7][0] LED[8][3] LED[8][2] LED[8][1] LED[8][0] MRXD[3] MRXD[2] MRXD[1] MRXD[0] CTRL EN1P Note: This is also controlled by the EEPROM registers (registers 4-12 bit 4). The values in the EEPROM supercede this pin. Also, if the priority selection is unaltered in the EEPROM registers (register 3 bits 0-7) then values above 3 are considered high priorty and less than 4 are low priority. MIIS[1:0] H MII mode selection - allows the MII to run in the following modes MIIS 10 0 0 1 1 Note 1. Operating mode Disable MII interface Reverse MII Forward MII 7 wire mode (SNI) 0 1 0 1 All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up. See "Reference Circuits" section. KS8999 16 January 2005 KS8999 Group I/O Names PRSV Active Status H Description(Note 1) Micrel Priority buffer reserve - reserves 6KB of buffer space for the priority traffic if enabled. 0 = No priority reserve 1 = Reserve 6KB for priority traffic Note: This is also controlled by the EEPROM registers (register 2 bit 1). The value in the EEPROM supercedes this pin. CFGMODE H Selects between EEPROM or processor for programming interface. 0 = Processor interface 1 = EEPROM interface or not programmed on this interface (SCL / SDA not used) External crystal or clock input Used when other polarity of crystal is needed. This is unused for a normal clock input. Clock for EEPROM Serial data for EEPROM System reset Factory test input - tie low for normal operation Factory test input - tie low for normal operation Factory test input - leave open for normal operation Factory test output - leave open for normal operation Factory test output - leave open for normal operation Factory test output - leave open for normal operation Factory test output - leave open for normal operation Factory test output - leave open for normal operation Factory test output - leave open for normal operation Factory test output - leave open for normal operation Factory test output - leave open for normal operation Factory test inputs - leave open for normal operation F/U = Enable Auto MDI/MDIX (normal operation) D = Disable Auto MDI/MDIX Factory test inputs - leave open (float) for normal operation F/D = normal operation (default) U = Disable FEF Factory test outputs - leave open for normal operation Factory test outputs - leave open for normal operation Factory test input - tie high for normal operation Factory test input - tie low for normal operation Factory test input - tie low for normal operation 2.0V for equalizer Ground for equalizer 2.0V for transmit circuitry Ground for transmit circuitry 2.0V for clock recovery circuitry Ground for clock recovery 2.0V for phase locked loop circuitry X1 X2 SCL SDA RST# TEST TESTEN SCANEN MUX[1:2] AOUT DOUT AOUT2 DOUT2 BTOUT CTOUT BTOUT2 CTOUT2 TEST[1:2] AUTOMDIX T[1:3] & T[5] T[4] QH[2:5] QL[2:5] IO_SWM RLPBK BIST PWR VDD_RX GND_RX VDD_TX GND_TX VDD_RCV GND_RCV VDD_PLLTX Note 1. Clock Clock Clock I/O L H H H H H H H H H H H H H H H H H H H H All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up. See "Reference Circuits" section. January 2005 17 KS8999 KS8999 Group I/O Names GND_PLLTX GND-ISO VDD VDD-IO GND Active Status Description Ground for phase locked loop circuitry Analog ground 2.0V for core digital circuitry 2.0V, 2.5V or 3.3V for I/O circuitry Ground for digital circuitry Micrel KS8999 18 January 2005 KS8999 Micrel Pin Configuration IO_SWM GND GND LED[8][0] LED[8][1] LED[8][2] LED[8][3] LED[7][0] VDD_IO LED[7][1] LED[7][2] LED[7][3] LED[6][0] LED[6][1] LED[6][2] LED[6][3] LED[5][0] LED[5][1] LED[5][2] LED[5][3] GND VDD LED[4][0] LED[4][1] LED[4][2] LED[4][3] LED[3][0] LED[3][1] LED[3][2] LED[3][3] GND VDD_IO MRXC MRXD[0] MRXD[1] MRXD[2] MRXD[3] MRXDV LED[2][0] LED[2][1] LED[2][2] LED[2][3] LED[1][0] LED[1][1] LED[1][2] LED[1][3] RST# BIST VDD GND GND VDD_IO 105 VDD LED[9][3] LED[9][2] LED[9][1] LED[9][0] MIIS[1] MIIS[0] MODESEL[3] MODESEL[2] MODESEL[1] MODESEL[0] TESTEN SCANEN PRSV CFGMODE T[5] T[4] RESERVE RESERVE X1 X2 VDD_PLLTX GND_PLLTX CTOUT BTOUT VDD_RCV VDD_RCV GND_RCV GND_RCV VDD_RCV VDD_RCV GND_RCV GND_RCV FXSD[1] FXSD[2] FXSD[3] FXSD[4] VDD_RX GND_RX RXP[1] RXM[1] GND_TX TXP[1] TXM[1] VDD_TX VDD_TX TXP[2] TXM[2] GND_TX RXP[2] RXM[2] GND_ISO 157 53 1 MCRS MCOL MTXC MTXER MTXD[0] MTXD[1] MTXD[2] MTXD[3] MTXEN GND VDD SCL SDA EN1P T[3] T[2] T[1] AUTOMDIX TEST[2] TEST[1] MUX[2] MUX[1] RLPBK CTOUT2 BTOUT2 VDD_RCV VDD_RCV GND_RCV GND_RCV VDD_RCV VDD_RCV GND_RCV GND_RCV FXSD[8] FXSD[7] FXSD[6] FXSD[5] VDD_RX GND_RX RXM[8] RXP[8] GND_TX TXM[8] TXP[8] VDD_TX VDD_TX TXM[7] TXP[7] GND_TX RXM[7] RXP[7] GND_ISO January 2005 VDD_RX GND_RX GND_RX VDD_RX RXP[3] RXM[3] AOUT2 DOUT[2] TXP[3] TXM[3] QH[5] QH[4] QH[3] QH[2] GND_TX VDD_TX VDD_TX GND_ISO TXP[4] TXM[4] GND_TX RXP[4] RXM[4] GND_RX VDD_RX ISET GND_ISO VDD_RX GND_RX RXP[5] RXM[5] GND_TX TXP[5] TXM[5] GND_ISO VDD_TX VDD_TX GND_TX QL[2] QL[3] QL[4] QL[5] TXP[6] TXM[6] DOUT AOUT RXP[6] RXM[6] VDD_RX GND_RX GND_RX VDD_RX 208-Pin PQFP (PQ) 19 KS8999 KS8999 Micrel Functional Overview: Physical Layer Transceiver 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, then transmitted in MLT3 current output. The output current is set by an external 1% 3.01k resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4 ns and complies to the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitters. The waveshaped 10BaseT output is also incorporated into the 100BaseTX transmitter. 100BaseTX Receive The 100BaseTX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial to parallel conversion. The receiving side starts with the equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. This is an ongoing process and can self adjust to the environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is provided as the input data to the MAC. PLL Clock Synthesizer The KS8999 generates 125MHz, 62.5MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal. Scrambler/De-scrambler (100BaseTX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled by the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100BaseFX Operation 100BaseFX operation is very similar to 100BaseTX operation with the differences being that the scrambler/de-scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation. 100BaseFX Signal Detection The physical port runs in 100BaseFX mode if FXSDx >0.6V. FXSDx is considered `low' when 0.6V 100BaseFX Far End Fault Far end fault occurs when the signal detection is logically false from the receive fiber module which occurs when FXSDx is below 1.2V and above 0.6V. When this occurs, the transmission side signals the other end of the link by sending 84 1's followed by a zero in the idle period between frames. 10BaseT Transmit The output 10BaseT driver is incorporated into the 100BaseT driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. 10BaseT Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8999 decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. KS8999 20 January 2005 KS8999 Micrel Power Management Power Save Mode The KS8999 will turn off everything except for the Energy Detect and PLL circuits when the cable is not installed on an individual port basis. In other words, the KS8999 will shutdown most of the internal circuits to save power if there is no link. MDI/MDI-X Auto Crossover The KS8999 supports MDI/MDI-X auto crossover. This facilitates the use of either a straight connection CAT-5 cable or a crossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the Micrel device. This can be highly useful when end users are unaware of cable types and can also save on an additional uplink configuration connection. The auto MDI/MDI-X is achieved by the Micrel device listening for the far end transmission channel and assigning transmit/ receive pairs accordingly. Auto MDI/MDI-X can be disabled by pulling the pin 87 (AUTOMDIX) to low. Auto-Negotiation The KS8999 conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto-negotiation the link partners advertise capabilities across the link to each other. If auto-negotiation is not supported or the link partner to the KS8999 is forced to bypass auto-negotiation , then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto-negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The flow for the link set up is depicted below. Start Auto Negotiation Force Link Setting No Parallel Operation Yes Bypass Auto-Negotiation and Set Link Mode Attempt Auto-Negotiation Listen for 100BaseTX Idles Listen for 10BaseT Link Pulses No Join Flow Link Mode Set ? Yes Link Mode Set Figure 2. Auto-Negotiation January 2005 21 KS8999 KS8999 Micrel Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains 1K full CAM with 48-bit address plus switching information. The KS8999 is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal look-up engine will update its table with a new entry if the following conditions are met: * The received packet's SA does not exist in the look-up table. * The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will insert the qualified SA into the table, along with the port number, time stamp. If the table is full, the last entry of the table will be deleted first to make room for the new entry. Migration The internal look-up engine also monitors whether a station is moved. If it happens, it will update the table accordingly. Migration happens when the following conditions are met: * The received packet's SA is in the table but the associated source port information is different. * The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will update the existing record in the table with the new source port information. Aging The look-up engine will update time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will then remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 seconds. This feature can be enabled or disabled by external pull-up or pull-down resistors. Forwarding The KS8999 will forward packets as follows: * If the DA look-up results is a "match", the KS8999 will use the destination port information to determine where the packet goes. * If the DA look-up result is a "miss", the KS8999 will forward the packet to all other ports except the port that received the packet. * All the multicast and broadcast packets will be forwarded to all other ports except the source port. The KS8999 will not forward the following packets: * Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. * 802.3x pause frames. The KS8999 will intercept these packets and do the appropriate actions. * "Local" packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches the port where the packet was from, the packet is defined as "local". Switching Engine The KS8999 has a very high performance switching engine to move data to and from the MAC's, packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8999 has an internal buffer for frames that is 32Kx32 (128KB). This resource could be shared between the nine ports and is programmed at system reset time by using the unmanaged program mode (I/O strapping). Each buffer is sized at 128B and therefore there are a total of 1024 buffers available. Two different modes are available for buffer allocation. One mode equally allocates the buffers to all the ports (113 buffers per port). The other mode adaptively allocates buffers up to 512 to a single port based on loading. Selection is achieved by using LED[7][1] in the unmanaged programming description. MAC Operation The KS8999 strictly abides by IEEE 802.3 standard to maximize compatibility. Inter Packet Gap (IPG) If a frame is successfully transmitted, the 96 bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96 bit time IPG is measured from MCRS and the next MTXEN. KS8999 22 January 2005 KS8999 Backoff Algorithm Micrel The KS8999 implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional "aggressive mode" back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration. Late Collision If a transmit packet experiences collisions after 512 bit times of the transmission, the packet will be dropped. Illegal Frames The KS8999 discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes. Since the KS8999 supports VLAN tags, the maximum sizing is adjusted when these tags are present. Flow Control The KS8999 supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8999 receives a pause control frame, the KS8999 will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KS8999 will be transmitted. On the transmit side, the KS8999 has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8999 will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8999 will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8999 will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent flow control mechanism from being activated and deactivated too many times. The KS8999 will flow control all ports if the receive queue becomes full. Half Duplex Back Pressure Half duplex back pressure option (Note: not in 802.3 standards) is also provided. The activation and deactivation conditions are the same as the above in full duplex mode. If back pressure is required, the KS8999 will send preambles to defer other stations' transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier sense type back pressure will be interrupted and those packets will be transmitted instead. If there are no more packets to send, carrier sense type back pressure will be active again until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. Broadcast Storm Protection The KS8999 has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus will use too many switch resources (bandwidth and available space in transmit queues). The KS8999 will discard broadcast packets if the number of those packets exceeds the threshold (configured by strapping during reset and EEPROM settings) in a preset period of time. If the preset period expires it will then resume receiving broadcast packets until the threshold is reached. The options are 5% of network line rate for the maximum broadcast receiving threshold or unlimited (feature off). January 2005 23 KS8999 KS8999 Micrel MII Interface Operation The MII (Media Independent Interface) operates in either a MAC or PHY mode. In the MAC mode, the KS8999 MII acts like a MAC and in the PHY mode, it acts like a PHY device. This interface is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. There are two distinct groups, one being for transmission and the other for receiving. The table below describes the signals used in this interface in MAC and PHY modes. PHY Mode Connection External MAC Controller Signals MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8999 PHY Signals MTXEN MTXER MTXD[3] MTXD[2] MTXD[1] MTXD[0] MTXC MCOL MCRS MRXDV Not used MRXD[3] MRXD[2] MRXD[1] MRXD[0] MRXC Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock MAC Mode Connection External PHY Signals MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8999 MAC Signals MRXDV Not used MRXD[3] MRXD[2] MRXD[1] MRXD[0] MTXC MCOL MCRS SMTXEN MTXER MTXD[3] MTXD[2] MTXD[1] MTXD[0] MRXC Table 1. MII Signals This interface is a nibble wide data interface and therefore runs at _ the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicates a collision has occurred during transmission. KS8999 24 January 2005 KS8999 Micrel Note that the signal MRXER is not provided on the MII interface for the KS8999 for PHY mode operation and MTXER is not represented for MAC mode. Normally this would indicate a receive / transmit error coming from the physical layer /MAC device, but is not appropriate for this configuration. If the connecting device has a MRXER pin, this should be tied low on the other device for reverse or if it has a MTXER pin in the forward mode it should also be tied low on the other device. The following explains the KS8999 in PHY mode and MAC mode of operation: KS8999 PHY Mode MTXC External MAC Controller MTXD[3:0] MTXEN KS8999 In PHY mode MTXER Figure 3. Data Sent from External MAC Controller to KS8999 PHY Mode MRXC External MAC Controller MRXD[3:0] MRXEN KS8999 In PHY Mode Figure 4. Data Sent from PHY Mode to External MAC Controller KS8999 MAC Mode MRXC KS8999 In MAC mode MTXD[3:0] External PHY MTXEN MTXER Figure 5. Data Sent from PHY Device to KS8999 MAC Mode MTXC KS8999 In MAC Mode MRXD[3:0] External PHY MRXDV Figure 6. Data Sent from KS8999 PHY Mode to External PHY Device January 2005 25 KS8999 KS8999 Micrel SNI Interface (7-wire) Operation The SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. KS8999 acts like a PHY device to external controllers. This interface can be directly connected to these types of devices. The signals are divided into two groups, one being for transmission and the other being the receive side. The signals involved are described in the table below. SNI Signal TXEN TXD TXC COL CRS RXD RXC Description Transmit enable Serial transmit data Transmit clock Collision detection Carrier sense Serial receive data Receive clock KS8999 SNI Signal MTXEN MTXD[0] MTXC MCOL MRXDV MRXD[0] MRXC KS8999 Input/Output Input Input Output Output Output Output Output Table 2. SNI Signals This interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid. For half-duplex operation there is a signal that indicate a collision has occurred during transmission. Programmable Features Priority Schemes The KS8999 can determine priority through three different means at the ingress point. The first method is a simple per port method, the second is via the 802.1p frame tag and the third is by viewing the DSCP (TOS) field in the IPv4 header. Of course for the priority to be effective, the high and low priority queues must be enabled on the destination port or egress point. Per Port Method General priority can be specified on a per port basis. In this type of priority all traffic from the specified input port is considered high priority in the destination queue. This can be useful in IP phone applications mixed with other data types of traffic where the IP phone connects to a specific port. The IP phone traffic would be high priority (outbound) to the wide area network. The inbound traffic to the IP phone is all of the same priority to the IP phone. 802.1p Method This method works well when used with ports that have mixed data and media flows. The inbound port examines the priority field in the tag and determines the high or low priority. Priority profiles are setup in the Priority Classification Control in the EEPROM. IPv4 DSCP Method This is another per frame way of determining outbound priority. The DSCP (Differentiated Services Code Point - RFC#2474) method uses the TOS field in the IP header to determine high and low priority on a per code point basis. Each fully decoded code point can have either a high or low priority. A larger spectrum of priority flows can be defined with this larger code space. More specific to implementation, the most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If the register bit is a 1, the priority is high and if 0, the priority is low. Other Priority Considerations When setting up the priority scheme, one should consider other available controls to regulate the traffic. One of these is Priority Control Scheme (register 2 bits 2-3) which controls the interleaving of high and low priority frames. Options allow from a 2:1 ratio up to a setting that sends all the high priority first. This setting controls all ports globally. Another global feature is Priority Buffer Reserve (register 2 bit 1). If this is set, there is a 6KB (10%) buffer dedicated to high priority traffic, otherwise if cleared the buffer is shared between all traffic. On an individual port basis there are controls that enable DSCP, 802.1p, port based and high/low priority queues. These are contained in registers 4-12 bits 5-3 and 0. It should be noted that there is a special pin that generally enables the 802.1p priority for all ports (pin 91). When this pin is active (high) all ports will have the 802.1p priority enabled unless specifically disabled by EEPROM programming (bit 4 of registers 4-12). Default high priority is a value greater than 4 in the VLAN tag with low priority being 3 or less. KS8999 26 January 2005 KS8999 Micrel The table below briefly summarizes priority features. For more detailed settings see the EEPROM register description. Register(s) Bit(s) Global/Port Description General 2 2 4-12 3-2 1 0 Global Global Port Priority Control Scheme: Transmit buffer high/low interleave control Priority Buffer Reserve: Reserves 6KB of the buffer for high priority traffic Enable Port Queue Split: Splits the transmit queue on the desired port for high and low priority traffic DSCP Priority 4-12 40-47 5 7-0 Port Global Enable Port DSCP: Looks at DSCP field in IP header to decide high or low priority DSCP Priority Points: Fully decoded 64 bit register used to determine priority from DSCP field (6 bits) in the IP header 802.1p Priority 4-12 3 4 7-0 Port Global Enable Port 802.1p Priority: Uses the 802.1p priority tag (3 bits) to determine frame priority Priority Classification: Determines which tag values have high priority Per Port Priority 4-12 3 Port Enable Port Priority: Determines which ports have high or low priority traffic Table 3. Priority Control VLAN Operation The VLAN's are setup by programming the VLAN Mask Registers in the EEPROM. The perspective of the VLAN is from the input port and which output ports it sees directly through the switch. For example if port 1 only participated in a VLAN with ports 2 and 9 then one would set bits 0 and 7 in register 13 (Port 1 VLAN Mask Register). Note that different ports can be setup independently. An example of this would be where a router is connected to port 9 and each of the other ports would work autonomously. In this configuration ports 1 through 8 would only set the mask for port 9 and port 9 would set the mask for ports1 through 8. In this way, the router could see all ports and each of the other individual ports would only communicate with the router. All multicast and broadcast frames adhere to the VLAN configuration. Unicast frame treatment is a function of register 2 bit 0. If this bit is set then unicast frames only see ports within their VLAN. If this bit is cleared unicast frames can traverse VLAN's. VLAN tags can be added or removed on a per port basis. Further, there are provisions to specify the tag value to be inserted on a per port basis. The table below briefly summarizes VLAN features. For more detailed settings see the EEPROM register description. Register(s) 4-12 4-12 2 13-21 22-39 Bit(s) 2 1 0 7-0 7-0 Global/Port Port Port Global Port Port Description Insert VLAN Tags: If specified, will add VLAN tags to frames without existing tags Strip VLAN Tags: If specified, will remove VLAN tags from frames if they exist VLAN Enforcement: Allows unicast frames to adhere or ignore the VLAN configuration VLAN Mask Registers: Allows configuration of individual VLAN grouping. VLAN Tag Insertion Values: Specifies the VLAN tag to be inserted if enabled (see above) Table 4. VLAN Control Station MAC Address (control frames only) The MAC source address can be programmed as used in flow control frames. The table below briefly summarizes this programmable feature. Register(s) 48-53 Bit(s) 7-0 Global/Port Global Description Station MAC Address: Used as source address for MAC control frames as used in full duplex flow control mechanisms. Table 5. Misc. Control January 2005 27 KS8999 KS8999 Micrel EEPROM Operation The EEPROM interface utilizes 2 pins that provide a clock and a serial data path. As part of the initialization sequence, the KS8999 reads the contents of the EEPROM and loads the values into the appropriate registers. Note that the first two bytes in the EEPROM must be "55" and "99" respectively for the loading to occur properly. If these first two values are not correct, all other data will be ignored. Data start and stop conditions are signaled on the data line as a state transition during clock high time. A high to low transition indicates start of data and a low to high transition indicates a stop condition. The actual data that traverses the serial line changes during the clock low time. The KS8999 EEPROM interface is compatible with the Atmel AT24C01A part. Address A0, A1 and A2 are fixed to 000. Further timing and data sequences can be found in the Atmel AT24C01A specification. Optional CPU Interface Instead of using an EEPROM to program the KS8999, one can use an external processor. To utilize this feature, the CFGMODE pin (only available on the 208 pin package) needs to pulled low. This makes the KS8999 serial and clock interface into a slave rather than a master. In this mode, clock and data are sourced from the processor. Due to timing constraints, the maximum clock speed that the processor can generate is 8MHz. Data timing is referenced to the rising edge of the clock and are 10ns for setup and 60ns for hold. The processor needs to supply the exact number of clock cycles and data bits to program the KS8999 properly. KS8999 won't start until all of the registers are programmed. Bits are loaded from high order (bit 7) to low order (bit 0) starting with register 0 and finishing with register 53. Register 0: Skip clock on first bit 7 SCL clock cycle: 7 Register 1 to Register 53: provide clock on bit 7 to bit 0 SCL clock cycle: 424 Total SCL clock cycle: 431 SCL SDA B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 Register 1 Register 0 KS8999 28 January 2005 KS8999 Micrel EEPROM Memory Map Address 0 1 Name 7-0 7-0 Description Signature byte 1. Value = "55" Signature byte 2. Value = "99" Default (chip) Value 0x55 0x99 General Control Register 2 2 7-4 3-2 Reserved - set to zero Priority control scheme (all ports) 00 = Transmit all high priority before any low priority 01= Transmit high and low priority at a 10:1 ratio 10 = Transmit high and low priority at a 5:1 ratio 11 = Transmit high and low priority at a 2:1 ratio Priority buffer reserve for high priority traffic 1 = Reserve 6KB of buffer space for high priority 0 = None reserved VLAN enforcement 1 = All unicast frames adhere to VLAN configuration 0 = Unicast frames ignore VLAN configuration 0000 00 2 1 0 2 0 0 Priority Classification Control - 802.1p tag field 3 3 3 3 3 3 3 3 7 6 5 4 3 2 1 0 1 = State "111" is high priority 0 = State "111" is low priority 1 = State "110" is high priority 0 = State "110" is low priority 1 = State "101" is high priority 0 = State "101" is low priority 1 = State "100" is high priority 0 = State "100" is low priority 1 = State "011" is high priority 0 = State "011" is low priority 1 = State "010" is high priority 0 = State "010" is low priority 1 = State "001" is high priority 0 = State "001" is low priority 1 = State "000" is high priority 0 = State "000" is low priority 1 1 1 1 0 0 0 0 Port 1 Control Register 4 4 7-6 5 Reserved - set to zero TOS priority classification enable for port 1 1 = Enable 0 = Disable 802.1p priority classification enable for port 1 1 = Enable 0 = Disable Port based priority classification for port 1 1 = High priority 0 = Low priority Insert VLAN tags for port 1 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 1 if existent 1 = Enable 0 = Disable 00 0 4 4 0 4 3 0 4 2 0 4 1 0 January 2005 29 KS8999 KS8999 Address 4 Name 0 Description Enable high and low output priority queues for port 1 1 = Enable 0 = Disable Default (chip) Value 0 Micrel Port 2 Control Register 5 5 7-6 5 Reserved - set to zero TOS priority classification enable for port 2 1 = Enable 0 = Disable 802.1p priority classification enable for port 2 1 = Enable 0 = Disable Port based priority classification for port 2 1 = High priority 0 = Low priority Insert VLAN tags for port 2 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 2 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 2 1 = Enable 0 = Disable 00 0 5 4 0 5 3 0 5 2 0 5 1 0 5 0 0 Port 3 Control Register 6 6 7-6 5 Reserved - set to zero TOS priority classification enable for port 3 1 = Enable 0 = Disable 802.1p priority classification enable for port 3 1 = Enable 0 = Disable Port based priority classification for port 3 1 = High priority 0 = Low priority Insert VLAN tags for port 3 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 3 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 3 1 = Enable 0 = Disable 00 0 6 4 0 6 3 0 6 2 0 6 1 0 6 0 0 Port 4 Control Register 7 7 7-6 5 Reserved - set to zero TOS priority classification enable for port 4 1 = Enable 0 = Disable 802.1p priority classification enable for port 4 1 = Enable 0 = Disable 00 0 7 4 0 KS8999 30 January 2005 KS8999 Address 7 Name 3 Description Port based priority classification for port 4 1 = High priority 0 = Low priority Insert VLAN tags for port 4 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 4 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 4 1 = Enable 0 = Disable Default (chip) Value 0 Micrel 7 2 0 7 1 0 7 0 0 Port 5 Control Register 8 8 7-6 5 Reserved - set to zero TOS priority classification enable for port 5 1 = Enable 0 = Disable 802.1p priority classification enable for port 5 1 = Enable 0 = Disable Port based priority classification for port 5 1 = High priority 0 = Low priority Insert VLAN tags for port 5 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 5 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 5 1 = Enable 0 = Disable 00 0 8 4 0 8 3 0 8 2 0 8 1 0 8 0 0 Port 6 Control Register 9 9 7-6 5 Reserved - set to zero TOS priority classification enable for port 6 1 = Enable 0 = Disable 802.1p priority classification enable for port 6 1 = Enable 0 = Disable Port based priority classification for port 6 1 = High priority 0 = Low priority Insert VLAN tags for port 6 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 6 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 6 1 = Enable 0 = Disable 00 0 9 4 0 9 3 0 9 2 0 9 1 0 9 0 0 January 2005 31 KS8999 KS8999 Address Name Description Default (chip) Value Micrel Port 7 Control Register 10 10 7-6 5 Reserved - set to zero TOS priority classification enable for port 7 1 = Enable 0 = Disable 802.1p priority classification enable for port 7 1 = Enable 0 = Disable Port based priority classification for port 7 1 = High priority 0 = Low priority Insert VLAN tags for port 7 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 7 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 7 1 = Enable 0 = Disable 00 0 10 4 0 10 3 0 10 2 0 10 1 0 10 0 0 Port 8 Control Register 11 11 7-6 5 Reserved - set to zero TOS priority classification enable for port 8 1 = Enable 0 = Disable 802.1p priority classification enable for port 8 1 = Enable 0 = Disable Port based priority classification for port 8 1 = High priority 0 = Low priority Insert VLAN tags for port 8 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 8 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 8 1 = Enable 0 = Disable 00 0 11 4 0 11 3 0 11 2 0 11 1 0 11 0 0 Port 9 Control Register 12 12 7-6 5 Reserved - set to zero TOS priority classification enable for port 9 1 = Enable 0 = Disable 802.1p priority classification enable for port 9 1 = Enable 0 = Disable Port based priority classification for port 9 1 = High priority 0 = Low priority 00 0 12 4 0 12 3 0 KS8999 32 January 2005 KS8999 Address 12 Name 2 Description Insert VLAN tags for port 9 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 9 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 9 1 = Enable 0 = Disable Default (chip) Value 0 Micrel 12 1 0 12 0 0 Port 1 VLAN Mask Register 13 7 Port 9 inclusion 1 = Port 9 in the same VLAN as port 1 0 = Port 9 not in the same VLAN as port 1 Port 8 inclusion 1 = Port 8 in the same VLAN as port 1 0 = Port 8 not in the same VLAN as port 1 Port 7 inclusion 1 = Port 7 in the same VLAN as port 1 0 = Port 7 not in the same VLAN as port 1 Port 6 inclusion 1 = Port 6 in the same VLAN as port 1 0 = Port 6 not in the same VLAN as port 1 Port 5 inclusion 1 = Port 5 in the same VLAN as port 1 0 = Port 5 not in the same VLAN as port 1 Port 4 inclusion 1 = Port 4 in the same VLAN as port 1 0 = Port 4 not in the same VLAN as port 1 Port 3 inclusion 1 = Port 3 in the same VLAN as port 1 0 = Port 3 not in the same VLAN as port 1 Port 2 inclusion 1 = Port 2 in the same VLAN as port 1 0 = Port 2 not in the same VLAN as port 1 1 13 6 1 13 5 1 13 4 1 13 3 1 13 2 1 13 1 1 13 0 1 Port 2 VLAN Mask Register 14 7 Port 9 inclusion 1 = Port 9 in the same VLAN as port 2 0 = Port 9 not in the same VLAN as port 2 Port 8 inclusion 1 = Port 8 in the same VLAN as port 2 0 = Port 8 not in the same VLAN as port 2 Port 7 inclusion 1 = Port 7 in the same VLAN as port 2 0 = Port 7 not in the same VLAN as port 2 Port 6 inclusion 1 = Port 6 in the same VLAN as port 2 0 = Port 6 not in the same VLAN as port 2 Port 5 inclusion 1 = Port 5 in the same VLAN as port 2 0 = Port 5 not in the same VLAN as port 2 Port 4 inclusion 1 = Port 4 in the same VLAN as port 2 0 = Port 4 not in the same VLAN as port 2 1 14 6 1 14 5 1 14 4 1 14 3 1 14 2 1 January 2005 33 KS8999 KS8999 Address 14 Name 1 Description Port 3 inclusion 1 = Port 3 in the same VLAN as port 2 0 = Port 3 not in the same VLAN as port 2 Port 1 inclusion 1 = Port 1 in the same VLAN as port 2 0 = Port 1 not in the same VLAN as port 2 Default (chip) Value 1 Micrel 14 0 1 Port 3 VLAN Mask Register 15 7 Port 9 inclusion 1 = Port 9 in the same VLAN as port 3 0 = Port 9 not in the same VLAN as port 3 Port 8 inclusion 1 = Port 8 in the same VLAN as port 3 0 = Port 8 not in the same VLAN as port 3 Port 7 inclusion 1 = Port 7 in the same VLAN as port 3 0 = Port 7 not in the same VLAN as port 3 Port 6 inclusion 1 = Port 6 in the same VLAN as port 3 0 = Port 6 not in the same VLAN as port 3 Port 5 inclusion 1 = Port 5 in the same VLAN as port 3 0 = Port 5 not in the same VLAN as port 3 Port 4 inclusion 1 = Port 4 in the same VLAN as port 3 0 = Port 4 not in the same VLAN as port 3 Port 2 inclusion 1 = Port 2 in the same VLAN as port 3 0 = Port 2 not in the same VLAN as port 3 Port 1 inclusion 1 = Port 1 in the same VLAN as port 3 0 = Port 1 not in the same VLAN as port 3 1 15 6 1 15 5 1 15 4 1 15 3 1 15 2 1 15 1 1 15 0 1 Port 4 VLAN Mask Register 16 7 Port 9 inclusion 1 = Port 9 in the same VLAN as port 4 0 = Port 9 not in the same VLAN as port 4 Port 8 inclusion 1 = Port 8 in the same VLAN as port 4 0 = Port 8 not in the same VLAN as port 4 Port 7 inclusion 1 = Port 7 in the same VLAN as port 4 0 = Port 7 not in the same VLAN as port 4 Port 6 inclusion 1 = Port 6 in the same VLAN as port 4 0 = Port 6 not in the same VLAN as port 4 Port 5 inclusion 1 = Port 5 in the same VLAN as port 4 0 = Port 5 not in the same VLAN as port 4 Port 3 inclusion 1 = Port 3 in the same VLAN as port 4 0 = Port 3 not in the same VLAN as port 4 Port 2 inclusion 1 = Port 2 in the same VLAN as port 4 0 = Port 2 not in the same VLAN as port 4 1 16 6 1 16 5 1 16 4 1 16 3 1 16 2 1 16 1 1 KS8999 34 January 2005 KS8999 Address 16 Name 0 Description Port 1 inclusion 1 = Port 1 in the same VLAN as port 4 0 = Port 1 not in the same VLAN as port 4 Default (chip) Value 1 Micrel Port 5 VLAN Mask Register 17 7 Port 9 inclusion 1 = Port 9 in the same VLAN as port 5 0 = Port 9 not in the same VLAN as port 5 Port 8 inclusion 1 = Port 8 in the same VLAN as port 5 0 = Port 8 not in the same VLAN as port 5 Port 7 inclusion 1 = Port 7 in the same VLAN as port 5 0 = Port 7 not in the same VLAN as port 5 Port 6 inclusion 1 = Port 6 in the same VLAN as port 5 0 = Port 6 not in the same VLAN as port 5 Port 4 inclusion 1 = Port 4 in the same VLAN as port 5 0 = Port 4 not in the same VLAN as port 5 Port 3 inclusion 1 = Port 3 in the same VLAN as port 5 0 = Port 3 not in the same VLAN as port 5 Port 2 inclusion 1 = Port 2 in the same VLAN as port 5 0 = Port 2 not in the same VLAN as port 5 Port 1 inclusion 1 = Port 1 in the same VLAN as port 5 0 = Port 1 not in the same VLAN as port 5 1 17 6 1 17 5 1 17 4 1 17 3 1 17 2 1 17 1 1 17 0 1 Port 6 VLAN Mask Register 18 7 Port 9 inclusion 1 = Port 9 in the same VLAN as port 6 0 = Port 9 not in the same VLAN as port 6 Port 8 inclusion 1 = Port 8 in the same VLAN as port 6 0 = Port 8 not in the same VLAN as port 6 Port 7 inclusion 1 = Port 7 in the same VLAN as port 6 0 = Port 7 not in the same VLAN as port 6 Port 5 inclusion 1 = Port 5 in the same VLAN as port 6 0 = Port 5 not in the same VLAN as port 6 Port 4 inclusion 1 = Port 4 in the same VLAN as port 6 0 = Port 4 not in the same VLAN as port 6 Port 3 inclusion 1 = Port 3 in the same VLAN as port 6 0 = Port 3 not in the same VLAN as port 6 Port 2 inclusion 1 = Port 2 in the same VLAN as port 6 0 = Port 2 not in the same VLAN as port 6 Port 1 inclusion 1 = Port 1 in the same VLAN as port 6 0 = Port 1 not in the same VLAN as port 6 1 18 6 1 18 5 1 18 4 1 18 3 1 18 2 1 18 1 1 18 0 1 January 2005 35 KS8999 KS8999 Address Name Description Default (chip) Value Micrel Port 7 VLAN Mask Register 19 7 Port 9 inclusion 1 = Port 9 in the same VLAN as port 7 0 = Port 9 not in the same VLAN as port 7 Port 8 inclusion 1 = Port 8 in the same VLAN as port 7 0 = Port 8 not in the same VLAN as port 7 Port 6 inclusion 1 = Port 6 in the same VLAN as port 7 0 = Port 6 not in the same VLAN as port 7 Port 5 inclusion 1 = Port 5 in the same VLAN as port 7 0 = Port 5 not in the same VLAN as port 7 Port 4 inclusion 1 = Port 4 in the same VLAN as port 7 0 = Port 4 not in the same VLAN as port 7 Port 3 inclusion 1 = Port 3 in the same VLAN as port 7 0 = Port 3 not in the same VLAN as port 7 Port 2 inclusion 1 = Port 2 in the same VLAN as port 7 0 = Port 2 not in the same VLAN as port 7 Port 1 inclusion 1 = Port 1 in the same VLAN as port 7 0 = Port 1 not in the same VLAN as port 7 1 19 6 1 19 5 1 19 4 1 19 3 1 19 2 1 19 1 1 19 0 1 Port 8 VLAN Mask Register 20 7 Port 9 inclusion 1 = Port 9 in the same VLAN as port 8 0 = Port 9 not in the same VLAN as port 8 Port 7 inclusion 1 = Port 7 in the same VLAN as port 8 0 = Port 7 not in the same VLAN as port 8 Port 6 inclusion 1 = Port 6 in the same VLAN as port 8 0 = Port 6 not in the same VLAN as port 8 Port 5 inclusion 1 = Port 5 in the same VLAN as port 8 0 = Port 5 not in the same VLAN as port 8 Port 4 inclusion 1 = Port 4 in the same VLAN as port 8 0 = Port 4 not in the same VLAN as port 8 Port 3 inclusion 1 = Port 3 in the same VLAN as port 8 0 = Port 3 not in the same VLAN as port 8 Port 2 inclusion 1 = Port 2 in the same VLAN as port 8 0 = Port 2 not in the same VLAN as port 8 Port 1 inclusion 1 = Port 1 in the same VLAN as port 8 0 = Port 1 not in the same VLAN as port 8 1 20 6 1 20 5 1 20 4 1 20 3 1 20 2 1 20 1 1 20 0 1 KS8999 36 January 2005 KS8999 Address Name Description Default (chip) Value Micrel Port 9 VLAN Mask Register 21 7 Port 8 inclusion 1 = Port 8 in the same VLAN as port 9 0 = Port 8 not in the same VLAN as port 9 Port 7 inclusion 1 = Port 7 in the same VLAN as port 9 0 = Port 7 not in the same VLAN as port 9 Port 6 inclusion 1 = Port 6 in the same VLAN as port 9 0 = Port 6 not in the same VLAN as port 9 Port 5 inclusion 1 = Port 5 in the same VLAN as port 9 0 = Port 5 not in the same VLAN as port 9 Port 4 inclusion 1 = Port 4 in the same VLAN as port 9 0 = Port 4 not in the same VLAN as port 9 Port 3 inclusion 1 = Port 3 in the same VLAN as port 9 0 = Port 3 not in the same VLAN as port 9 Port 2 inclusion 1 = Port 2 in the same VLAN as port 9 0 = Port 2 not in the same VLAN as port 9 Port 1 inclusion 1 = Port 1 in the same VLAN as port 9 0 = Port 1 not in the same VLAN as port 9 1 21 6 1 21 5 1 21 4 1 21 3 1 21 2 1 21 1 1 21 0 1 Port 1 VLAN Tag Insertion Value Registers 22 22 22 23 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00 Port 2 VLAN Tag Insertion Value Registers 24 24 24 25 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00 Port 3 VLAN Tag Insertion Value Registers 26 26 26 27 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00 Port 4 VLAN Tag Insertion Value Registers 28 28 28 29 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00 January 2005 37 KS8999 KS8999 Address Name Description Default (chip) Value Micrel Port 5 VLAN Tag Insertion Value Registers 30 30 30 31 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00 Port 6 VLAN Tag Insertion Value Registers 32 32 32 33 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00 Port 7 VLAN Tag Insertion Value Registers 34 34 34 35 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00 Port 8 VLAN Tag Insertion Value Registers 36 36 36 37 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00 Port 9 VLAN Tag Insertion Value Registers 38 38 38 39 7-5 4 3-0 7-0 User priority [2:0] CFI VID [11:8] VID [7:0] 000 0 0x0 0x00 Diff Serv Code Point Registers 40 41 42 43 44 45 46 47 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 DSCP[63:56] DSCP[55:48] DSCP[47:40] DSCP[39:32] DSCP[31:24] DSCP[23:16] DSCP[15:8] DSCP[7:0] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Station MAC Address Registers (all ports - MAC control frames only) 48 49 50 51 52 53 Note: 7-0 7-0 7-0 7-0 7-0 7-0 MAC address [47:40] MAC address [39:32] MAC address [31:24] MAC address [23:16] MAC address [15:8] MAC address [7:0] 0x00 0x40 0x05 0x43 0x5E 0xFE The MAC address is reset to the value in the above table, but can set to any value via the EEPROM interface. This MAC address is used as the source address in MAC control frames that execute flow control between link peers. KS8999 38 January 2005 KS8999 Micrel Absolute Maximum Ratings (Note 1) Supply Voltage (VDD_RX, VDD_TX, VDD_RCV, VDD, VDD_PLLTX) .............................................. -0.5V to +2.3V (VDDIO) .................................................... -0.5V to +3.8V Input Voltage ............................................... -0.5V to +4.0V Output Voltage ............................................ -0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270C Storage Temperature (TS) ....................... -55C to +150C Operating Ratings (Note 2) Supply Voltage (VDD_RX, VDD_TX, VDD_RCV, VDD, VDD_PLLTX) .............................................. +2.0V to +2.3V (VDDIO) ....................... +2.0V to +2.3V or +3.0V to +3.6V Ambient Temperature (TA) Commercial .............................................. -0C to +70C Industrial ................................................. -40C to +85C Package Thermal Resistance, (Note 3) PQFP (JA) No Air Flow ................................... 39.1C/W Electrical Characteristics (KS8999) (Note 4) VDD = 2.0V to 2.3V; TA = 0C to +70; unless noted. Symbol VDD Parameter Supply Voltage Condition Min 2.00 Typ 2.10 Max 2.30 Units V Supply Current (including TX output driver current) 100BaseTX Operation--Total IDX IDA IDD IDX IDA IDD TTL Inputs VIH VIL IIN TTL Outputs VOH VOL |IOZ| VO VIMB tr, tt Output High Voltage Output Low Voltage Output Tri-State Leakage IOH = -4mA IOL = 4mA VDDIO -0.4 +0.4 10 V V A Input High Voltage Input Low Voltage Input Current VIN = GND ~ VDD -10 (1/2 VDDIO) +0.4 (1/2 VDDIO) -0.4 10 V V A 100BaseTX (Transmitter) 100BaseTX (Analog) 100BaseTX (Digital) 0.64 0.35 0.18 0.11 1.04 0.84 0.11 0.09 0.85 0.40 0.25 0.20 1.32 0.95 0.17 0.20 A A A A A A A A 10BaseT Operation--Total 100BaseTX (Transmitter) 100BaseTX (Analog) 100BaseTX (Digital) 100BaseTX Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance Note 1. Note 2. Note 3. Note 4. Exceeding the absolute maximum rating may damage the device. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD). No HS (heat spreader) in package. Specification for packaged product only. 50 from each output to VDD 50 from each output to VDD 0.95 1.05 2 V % ns ns 3 0 5 0.5 January 2005 39 KS8999 KS8999 Symbol Parameter Condition Min Typ Max 0.5 5 0.75 Peak-to-peak 0.7 1.4 Micrel Units 100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET Output Jitters 10BaseTX Receive VSQ VP Squelch Threshold 5MHz square wave 400 mV ns % V ns 10BaseT Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage Jitters Added Rise/Fall Times 50 from each output to VDD 50 from each output to VDD 28 2.3 3.5 V ns ns KS8999 40 January 2005 KS8999 Micrel Timing Diagrams tcyc SCL ts SDA th Figure 7. EEPROM Input Timing Symbol tCYC tS tH Parameter Clock Cycle Set-Up Time Hold Time 20 20 Min Typ 16384 Max Units ns ns ns Table 5. EEPROM Input Timing Parameters tcyc SCL tov SDA Figure 8. EEPROM Output Timing Symbol tCYC tOV Parameter Clock Cycle Output Valid 4096 Min Typ 16384 4112 4128 Max Units ns ns Table 6. EEPROM Output Timing Parameters January 2005 41 KS8999 KS8999 Micrel tcyc MTXC ts MTXD[0], MTXEN th Figure 9. SNI (7-wire) Input Timing Symbol tCYC tS tH Parameter Clock Cycle Set-Up Time Hold Time 10 0 Min Typ 100 Max Units ns ns ns Table 7. SNI (7-wire) Input Parameters tcyc MRXC tov MRXD[0], MRXDV, MCOL Figure 10. SNI (7-wire) Output Timing Symbol tCYC tOV Parameter Clock Cycle Output Valid Min Typ 100 Max Units ns 0 3 6 ns Table 8. SNI (7-wire) Output Timing Parameters KS8999 42 January 2005 KS8999 Micrel MTXC External MAC Controller MTXD[3:0] MTXEN KS8999 In PHY mode MTXER Figure 11. KS8999 PHY Mode--Data Sent from External MAC Controller to KS8999 tcyc MTXCLK ts MTXD[3:0] MTXEN MTXER th Figure 12. KS8999 PHY Mode Receive Timing Symbol tCYC tCYC tS tH Parameter Clock Cycle Clock Cycle Set-Up Time Hold Time (100BaseT) (10BaseT) Min Typ 40 400 Max Units ns ns ns ns 10 0 Table 9. MII Timing in KS8999 PHY and MAC Mode Timing Parameters January 2005 43 KS8999 KS8999 Micrel MRXC External MAC Controller MRXD[3:0] MRXEN KS8999 In PHY Mode Figure 13. KS8999 PHY Mode--Data Sent from KS8999 PHY Mode to External MAC Controller tcyc MRXCLK tov MRXD[3:0] MRXDV Figure 14. KS8999 PHY Mode Transmit Timing Symbol tCYC tCYC tOV Parameter Clock Cycle Clock Cycle Output Valid (100BaseT) (10BaseT) Min Typ 40 400 Max Units ns ns 18 25 28 ns Table 10. KS8999 PHY Mode Transmit Timing Parameters KS8999 44 January 2005 KS8999 Micrel MRXC KS8999 In MAC Mode MTXD[3:0] External PHY MTXEN MTXER Figure 15. KS8999 MAC Mode--Data Sent from External PHY Device to KS8999 tcyc MRXCLK ts MTXD[3:0] MTXEN MTXER th Figure 16. KS8999 MAC Mode Receive Timing Symbol tCYC tCYC tS tH Parameter Clock Cycle Clock Cycle Output Valid Output Valid (100BaseT) (10BaseT) Min Typ 40 400 Max Units ns ns ns ns 10 5 Table 11. KS8999 PHY Mode Transmit Timing Parameters January 2005 45 KS8999 KS8999 Micrel MTXC KS8999 In MAC Mode MRXD[3:0] External PHY MRXDV Figure 17. KS8999 MAC Mode Timing--Data Sent from KS8999 MAC mode to External PHY Device tcyc MTXCLK tov MRXD[3:0] MRXDV Figure 18. KS8999 MAC Mode Transmit Timing Symbol tCYC tCYC tOV Parameter Clock Cycle Clock Cycle Output Valid (100BaseT) (10BaseT) Min Typ 40 400 Max Units ns ns 7 11 16 ns Table 12. KS8999 MAC Mode Transmit Timing Parameters KS8999 46 January 2005 KS8999 Micrel Reference Circuits See "I/O Description" section for pull-up/pull-down and float information. VDD-IO Pull -up 10k LED pin 220 KS8999 VDD-IO Float 220 LED pin KS8999 VDD-IO Pull Down Pull-down 220 LED pin KS8999 1k Reference circuits for unmanaged programming through LED ports Note: For brighter LED operation use VDD-IO = 3.3V Figure 19. Unmanaged Programming Circuit Reset Reference Circuit Micrel recommendeds the following discrete reset circuit as shown in Figure 20 when powering up the KS8999 device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 21. VCC D1 KS8999 RST C 10F R 10k CPU/FPGA RST_OUT_n D2 D1, D2: 1N4148 Figure 20. Recommended Reset Circuit. January 2005 47 KS8999 KS8999 VCC D1: 1N4148 D1 KS8995X RST C 10F R 10k Micrel Figure 21. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KS8999 device. The reset out from CPU/ FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. KS8999 48 January 2005 KS8999 Micrel 4B/5B Coding In 100BaseTX and 100BaseFX the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4B/5B code. The extra code space is required to encode extra control (frame delineation) points. It is also used to reduce run length as well as supply sufficient transitions for clock recovery. The table below provides the translation for the 4B/5B coding. Code Type Data 4B Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Control Not defined 0101 0101 Not defined Not defined Not defined Invalid Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined 5B Code 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Value Data value 0 Data value 1 Data value 2 Data value 3 Data value 4 Data value 5 Data value 6 Data value 7 Data value 8 Data value 9 Data value A Data value B Data value C Data value D Data value E Data value F Idle Start delimiter part 1 Start delimiter part 2 End delimiter part 1 End delimiter part 2 Transmit error Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Table 13. 4B/5B Coding January 2005 49 KS8999 KS8999 Micrel MLT3 Coding For 100BaseTX operation the NRZI (Non-Return to Zero Invert on ones) signal is line coded as MLT3. The net result of using MLT3 is to reduce the EMI (Electro Magnetic Interference) of the signal over twisted pair media. In NRZI coding, the level changes from high to low or low to high for every "1" bit. For a "0" bit there is no transition. MLT3 line coding transitions through three distinct levels. For every transition of the NRZI signal the MLT3 signal either increments or decrements depending on the current state of the signal. For instance if the MLT3 level is at its lowest point the next two NRZI transitions will change the MLT3 signal initially to the middle level followed by the highest level (second NRZI transition). On the next NRZI change, the MLT3 level will decrease to the middle level. On the following transition of the NRZI signal the MLT3 level will move to the lowest level where the cycle repeats. The diagram below describes the level changes. Note that in the actual 100BaseTX circuit there is a scrambling circuit and that scrambling is not shown in this diagram. Hex Value Binary 4B Binary 5B A 3 8 E 9 4 T3 R3 I1 I1 1010 0011 1000 1110 1001 0100 UUUU UUUU UUUU UUUU 10110101011001011100100110101001101001111111111111 NRZ NRZI MLT3 Figure 20. MLT3 coding MAC Frame The MAC (Media Access Control) fields are described in the table below. Field Preamble/SFD DA SA Length Protocol/Data Frame CRC ESD Idle Octect Length 8 6 6 2 46 to 1500 4 1 Variable Description Preamble and Start of Frame Delimiter 48-bit Destination MAC Address 48-bit Source MAC Address Frame Length Higher Layer Protocol and Frame Data 32-bit Cyclical Redundancy Check End of Stream Delimiter Inter Frame Idles Table 14. MAC Frame KS8999 50 January 2005 KS8999 Micrel Selection of Isolation Transformer(Note 1) One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.) Note 1. Value 1 CT : 1 CT 350H 0.4H 12pF 0.9 1.0dB 1500Vrms Test Condition 100mV, 100 KHz, 8mA 1MHz (min.) 0MHz to 65MHz The IEEE 802.3u standard for 100BaseTX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value. Selection of Reference Oscillator/Crystal An oscillator or crystal with the following typical characteristics is recommended. Characteristics Name Frequency Maximum Frequency Tolerance Maximum Jitter Value 25.00000 50 150 Test Condition MHz ppm ps(pk-pk) The following transformer vendors provide compatible magnetic parts for Micrel's device: 4-Port Integrated Vendor Part Pulse Bel Fuse YCL Transpower Delta H1164 558-5999-Q9 PH406466 HB826-2 LF8731 Auto MDIX Yes Yes Yes Yes Yes Number of Port 4 4 4 4 4 Single Port Vendor Pulse Bel Fuse YCL Transpower Delta Part H1102 S558-5999-U7 PT163020 HB726 LF8505 Auto MDIX Yes Yes Yes Yes Yes Number of Port 1 1 1 1 1 Table 15. Qualified Magnetics Vendor Lists January 2005 51 KS8999 KS8999 Micrel Package Information 208-Pin PQFP (PQ) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL USA + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. KS8999 52 January 2005 |
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